1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Background Art
A Flash memory is one of nonvolatile semiconductor memories widely used at present. An example of the flash memory includes a NAND-type flash memory. A gate structure of the flash memory typically includes a first gate insulator called a tunnel insulator, a first gate electrode called a floating gate, a second gate insulator called an inter layer dielectric, and a second gate electrode called a control gate. An example of the flash memory having such gate structure is disclosed in JP-A2003-197779 (KOKAI).
A gate processing of the flash memory is often performed with a hard mask. In the case, an L/S (line and space) section, an SG (selection gate) section, and a peripheral Tr (transistor) section are generally processed with the same hard mask. The L/S section, the SG section, and the peripheral Tr section are provided with a cell transistor, a selection transistor, and another peripheral transistor respectively.
Recently, finer circuit patterns cause a very high aspect ratio in the gate structure of the flash memory. For this reason, when a gate processing is performed with a hard mask, there is a high possibility of causing a pattern collapse of the gate structure together with the hard mask. Therefore, a thinner hard mask has been required recently. The pattern collapse of the gate structure particularly tends to occur in the L/S section, because the L/S section significantly becomes finer, so that the aspect ratio of the gate structure in the L/S section is particularly high. Accordingly, it is desirable that the hard mask is as thin as possible, in view of preventing the pattern collapse of the gate structure.
On the other hand, it is necessary to form diffusion layers under source and drain regions in the peripheral Tr section, after the gate processing. The diffusion layers are formed to prevent depletion layers from extending to areas under the source and drain regions. This raises a punch through breakthrough voltage between transistors neighboring via an STI. The diffusion layers are formed by deeply implanting impurities with a high acceleration voltage. At this time, the hard mask prevents the impurities from being implanted in a channel region of the peripheral Tr section. However, if the hard mask is thin, the impurities penetrate the hard mask to be implanted in the channel region. This may give a bad influence on a channel profile. Accordingly, it is desirable that the hard mask is as thick as possible, in view of protecting the channel region.